LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 9

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Introduction
1
1.1
Datasheet
Introduction
The Dual-Core Intel® Xeon® Processor 3100 Series, like the previous Dual-Core Intel
Xeon
Intel Core microarchitecture combines the performance of previous generation
products with the power efficiencies of a low-power microarchitecture to enable
smaller, quieter systems. The Dual-Core Intel® Xeon® Processor 3100 Series is a 64-
bit processor that maintain compatibility with IA-32 software.
In this document, the Dual-Core Intel® Xeon® Processor 3100 Series may be referred
to simply as “the processor.”
The processors utilize Flip-Chip Land Grid Array (FC-LGA8) package technology, and
plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
The processor is a dual-core processor, based on 45 nm process technology. The
processor features the Intel
cache that significantly reduces latency to frequently used data. The processor features
a 1333 MHz front side bus (FSB) and 6 MB of L2 cache. The processor supports all the
existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3),
Supplemental Streaming SIMD Extension 3 (SSSE3), and the Streaming SIMD
Extensions 4.1 (SSE4.1). The processor supports several Advanced Technologies:
Execute Disable Bit, Intel
Intel
(Intel
The processor's front side bus (FSB) utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
®
®
®
Virtualization Technology (Intel
Processor 3000 Series, are based on the Intel
TXT).
®
64 architecture, Enhanced Intel SpeedStep
®
Advanced Smart Cache, a shared multi-core optimized
®
VT), and Intel
®
®
Core
Trusted Execution Technology
TM
microarchitecture. The
®
Technology,
®
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