LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 21

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
Figure 2-2.
2.6.4
2.7
Datasheet
V
Notes:
1.
2.
Die Voltage Validation
Overshoot events on processor must meet the specifications in
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are <
10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families. Design guidelines for the processor front
side bus are detailed in the appropriate platform design guides (refer to
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
platform design guidelines for details. Termination resistors (R
CC
V
T
Overshoot Example Waveform
OS
VID + 0.050
OS
VID - 0.000
is measured time duration above VID.
is measured overshoot voltage.
0
Table 2-13
5
for GTLREF specifications). Refer to the applicable
Example Overshoot Waveform
T
V
OS
OS
: Overshoot time above VID
: Overshoot above VID
10
T
Time [us]
OS
15
TT
. Because platforms implement
V
OS
TT
Table 2-5
) for GTL+ signals are
CC
20
and V
Section
when
TT
supplies
1.2).
25
21