LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 87

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Thermal Specifications and Design Considerations
5.3.1.1
Figure 5-5.
5.3.2
5.3.2.1
5.3.2.2
Datasheet
wide range (2Kbps to 2Mbps). The PECI interface on the processor is disabled by
default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
T
Fan speed control solutions based on PECI utilize a T
processor IA32_TEMPERATURE_TARGET MSR. The T
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the T
should utilize the relative temperature value delivered over PECI in conjunction with the
T
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Conceptual Fan Control Diagram on PECI-Based Platforms
PECI Specifications
PECI Device Address
The PECI register resides at address 0x30.
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Please refer to this document for details on supported PECI
command function and codes.
CONTROL
CONTROL
MSR value to control or optimize fan speeds.
and TCC activation on PECI-Based Systems
CONTROL
value as negative. Thermal management algorithms
CONTROL
CONTROL
Figure 5-5
MSR uses the same offset
value stored in the
shows a conceptual
85