LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 71

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Land Listing and Signal Descriptions
Table 4-3.
Datasheet
Signal Description (Sheet 2 of 8)
BPRI#
BR0#
BSEL[2:0]
COMP[3:0], COMP8
D[63:0]#
DBI[3:0]#
Name
Output
Output
Analog
Output
Output
Input/
Input/
Input/
Type
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor FSB. It must connect the appropriate pins/lands of all processor
FSB agents. Observing BPRI# active (as asserted by the priority agent)
causes all other agents to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by de-
asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the processor
to request the bus. During power-on configuration this signal is sampled to
determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the
processor input clock frequency.
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset
and clock synthesizer. All agents must operate at the same frequency. For
more information about these signals, including termination
recommendations refer to
guidelines.
COMP[3:0] and COMP8 must be terminated to V
precision resistors. Refer to the appropriate platform design guide for details
on implementation.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
path between the processor FSB agents, and must connect the appropriate
pins/lands on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond
to a pair of one DSTBP# and one DSTBN#. The following table shows the
grouping of data signals to data strobes and DBI#.
Quad-Pumped Signal Groups
Furthermore, the DBI# signals determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DBI# signal. When the
DBI# signal is active, the corresponding data group is inverted and therefore
sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the
polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when
the data on the data bus is inverted. If more than half the data bits, within a
16-bit group, would have been asserted electrically low, the bus agent may
invert the data bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Data Group
Bus Signal
D[31:16]#
D[47:32]#
D[63:48]#
D[15:0]#
DBI3#
DBI2#
DBI1#
DBI0#
Section 2.9.2
Description
Table 2-15
and the appropriate platform design
Data Bus Signals
DSTBN#/
DSTBP#
defines the possible
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
0
1
2
3
SS
on the system board using
DBI#
0
1
2
3
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