LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 91

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Features
6.2.2.2
6.2.3
6.2.3.1
Datasheet
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT powerdown state must be enabled via the BIOS for the processor to remain
within its specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the BIOS Writer's Guide for Extended Stop Grant configuration information. Refer to
the sections below for details about the Stop Grant and Extended Stop Grant states.
Stop-Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
Section
6.2.4).
TT
) for minimum power drawn by the termination
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