DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 100

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS31256 256-Channel, High-Throughput HDLC Controller
buffers have been filled or wait until the completed packet data has been written. The DMA always
writes to the done queue when it has finished receiving a packet, even if the threshold has not been met.
Done-Queue Burst Writing
The DMA can write to the done queue in bursts, which allows for a more efficient use of the PCI bus.
The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the
PCI bus for more time-critical functions.
An internal FIFO stores up to eight done-queue descriptors (8 dwords as each descriptor occupies one
dword). The host must configure the FIFO for proper operation through the receive DMA queues-control
(RDMAQ) register (see the following).
When enabled through the receive done-queue FIFO-enable (RDQFE) bit, the done-queue FIFO does not
write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high
watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to the
done queue. Before it writes to the done queue, it checks (by examining the receive done-queue host read
pointer) to ensure the done queue has enough room to empty the done-queue FIFO. If the done queue
does not have enough room, then it only burst writes enough descriptors to keep from overflowing the
done queue. If the FIFO detects that there is no room for any descriptors to be written, it sets the status
bit for the receive DMA done-queue write error (RDQWE) in the status register for DMA (SDMA). It
does not write to the done queue nor does it increment the write pointer. In such a scenario, packets can
be lost and unrecoverable. If the done-queue FIFO can write descriptors to the done queue, it burst writes
them, increments the write pointer, and sets the status bit for the receive DMA done-queue write
(RDQW) in the status register for DMA (SDMA). See Section
5
for more details on status bits.
Done-Queue FIFO Flush Timer
To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the DMA uses the
receive done-queue FIFO flush timer (RDQFFT) to determine the maximum wait time between writes.
The RDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256. It is
only monitored by the DMA when the receive done-queue FIFO is enabled (RDQFE = 1). For a 33MHz
PCLK, the timer is decremented every 7.76µs. For a 25MHz clock, it is decremented every 10.24µs.
Each time the DMA writes to the done queue it resets the timer to the count placed into it by the host. On
initialization, the host sets a value into the RDQFFT that indicates the maximum time the DMA should
wait in between writes to the done queue. For example, with a PCLK of 33MHz, the range of wait times
is from 7.8µs (RDQFFT = 0001h) to 508ms (RDQFFT = FFFFh). With a PCLK of 25MHz, the wait
times range from 10.2µs (RDQFFT = 0001h) to 671ms (RDQFFT = FFFFh).
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