DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 93

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Empty Case
The receive free queue is considered empty when the read and write pointers are identical.
Receive Free-Queue Empty State
Full Case
The receive free queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Receive Free-Queue Full State
Table 9-D
receive free queue.
Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address
Calculation
Table 9-E. Receive Free-Queue Internal Address Storage
Note: Both RFQSBSA and RFQEA are not absolute addresses, i.e., the absolute end address is “Base + RFQEA x 8.”
read pointer >
Large
Small
Receive Free-Queue Base Address 0 (lower word)
Receive Free-Queue Base Address 1 (upper word)
Receive Free-Queue Large Buffer Host Write Pointer
Receive Free-Queue Large Buffer DMA Read Pointer
Receive Free-Queue Small Buffer Start Address
Receive Free-Queue Small Buffer Host Write Pointer
Receive Free-Queue Small Buffer DMA Read Pointer
Receive Free-Queue End Address
read pointer >
BUFFER
describes how to calculate the absolute 32-bit address of the read and write pointers for the
Absolute Address = Free Queue Base + Write Pointer x 8
Absolute Address = Free Queue Base + Read Pointer x 8
Absolute Address = Free Queue Base + Small Buffer Start x 8 + Write Pointer x 8
Absolute Address = Free Queue Base + Small Buffer Start x 8 + Read Pointer x 8
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
valid descriptor
valid descriptor
empty descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
REGISTER
< write pointer
< write pointer
ALGORITHM
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RFQLBWP
RFQSBWP
RFQLBRP
RFQSBSA
RFQSBRP
RFQBA0
RFQBA1
RFQEA
NAME
ADDRESS
070Ch
071Ch
0700h
0704h
0710h
0718h
0714h
0708h