DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 48

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
6.2 Port Register Descriptions
Receive-Side Control Bits (one each for all 16 ports)
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Invert Clock Enable (RICE)
Bit 1/Invert Data Enable (RIDE)
Bit 2/Invert Sync Enable (RISE)
Bit 3/V.54 Detector Reset (VRST). Toggling this bit from 0 to 1 and then back to 0 causes the internal V.54
detector to be reset and begin searching for the V.54 loop-up pattern. See Section
Bit 4/Sync Delay Bit 0 (RSD0); Bit 5/Sync Delay Bit 1 (RSD1). These two bits define the format of the sync
signal that is applied to the RS[n] input. These bits are ignored if the port has been configured to operate in an
unchannelized fashion (RUEN = 1).
Bit 6/Sync Select Bit 0 (RSS0); Bit 7/Sync Select Bit 1 (RSS1). These two bits select the mode in which each
port is to be operated. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate.
These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1).
0 = do not invert clock (normal mode)
1 = invert clock (inverted clock mode)
0 = do not invert data (normal mode)
1 = invert data (inverted data mode)
0 = do not invert sync pulse (normal mode)
1 = invert sync pulse (inverted sync pulse mode)
00 = sync pulse is 0 clocks early
01 = sync pulse is 1/2 clock early
10 = sync pulse is 1 clock early
11 = sync pulse is 2 clocks early
00 = T1 Mode (24 DS0 channels and 193 RC clocks between RS sync signals)
01 = E1 Mode (32 DS0 channels and 256 RC clocks between RS sync signals)
10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between RS sync signals)
11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between RS sync signals)
RCOFA
RSS1
15
7
0
0
RP[n]CR, where n = 0 to 15 for each port
Receive Port [n] Control Register
See the Register Map in Section 4.
RSS0
IERC
14
6
0
0
RSD1
VLB
13
5
0
0
RSD0
VTO
12
48 of 183
4
0
0
VRST
n/a
11
3
0
0
RISE
LLB
10
2
0
0
6.4
for more details.
RUEN
RIDE
1
0
9
0
RP[i]HS
RICE
0
8
0
0