DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 142

IC CTRLR HDLC 256-CHANNEL 256BGA

DS31256

Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS31256

Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Quantity
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Maxim Integrated
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Register Name:
Register Description:
Register Address:
MSB
Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The
vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh.
Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was
assigned by Dallas Semiconductor and is fixed at 3134h.
Register Name:
Register Description:
Register Address:
MSB
Note: Read-only bits in the PCMD1 register are underlined; all other bits are read-write.
The lower word (bits 0 to 15) of the PCMD1 register is the command portion and is used for the PCI bus control.
When all bits in the lower word are set to 0, the device is logically disconnected from the bus for all accesses,
except for accesses to the configuration registers. The upper word (bits 16 to 31) is the status portion and is used
for status information. Reads to the status portion behave normally but writes are unique in that bits can be reset
(i.e., forced to 0) but not set (i.e., forced to 1). A bit in the status portion is reset when a 1 is written to that bit
position. Bit positions that have 0 written to them do not reset.
STEPC
FBBCT
PPE
PARC
UDF
PSE
PVID1
PCI Vendor ID/Device ID Register 1
0x100h
PCMD1
PCI Command/Status Register 1
0x104h
Reserved (Read Only/Set to All Zeros)
MABT
66MHz
VGA
Vendor ID (Read Only/Set to EAh)
Vendor ID (Read Only/Set to 13h)
Device ID (Read Only/Set to 34h)
Device ID (Read Only/Set to 31h)
TABTM
MWEN
142 of 183
Reserved (Read Only/Set to All Zeros)
TABT
SCC
MASC
DTS1
FBBEN
DTS0
MSC
PARR
PSEC
LSB
LSB
IOC

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