DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 85

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
9.2 Receive Side
9.2.1 Overview
The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps
track of and decides where the DMA should place the incoming packet data. There are a set of
descriptors that get handed back and forth between the DMA and the host. Through these descriptors, the
host can inform the DMA where to place the packet data and the DMA can tell the host when the data is
ready to be processed.
The operation of the receive DMA has three main areas, as shown in
Table
incoming packet data. Associated with each free data buffer location is a free packet descriptor where the
DMA can write information to inform the host about the attributes of the packet data (i.e., status
information, number of bytes, etc.) that it outputs. To accommodate the various needs of packet data, the
host can quantize the free data buffer space into two different buffer sizes. The host sets the size of the
buffers through the receive large buffer size (RLBS) and the receive small buffer size (RSBS) registers.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 12/Large Buffer Select Bit (LBS0 to LBS12)
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 12/Small Buffer Select Bit (SBS0 to SBS12)
9-B. The host writes to the free-queue descriptors informing the DMA where it can place the
0000000000000 (0000h) = buffer size is 0 Bytes
1111111111100 (1FFCh) = buffer size is 8188 Bytes
0000000000000 (0000h) = buffer size is 0 Bytes
1111111111100 (1FFCh) = buffer size is 8188 Bytes
LBS7
SBS7
n/a
n/a
15
15
7
0
0
7
0
0
RLBS
Receive Large Buffer Size Select
0790h
RSBS
Receive Small Buffer Size Select
0794h
LBS6
SBS6
n/a
n/a
14
14
6
0
0
6
0
0
LBS5
SBS5
n/a
n/a
13
13
5
0
0
5
0
0
LBS12
SBS12
LBS4
SBS4
12
12
85 of 183
4
0
0
4
0
0
LBS11
SBS11
LBS3
SBS3
11
11
3
0
0
3
0
0
LBS10
SBS10
LBS2
SBS2
10
10
2
0
0
2
0
0
Figure
LBS1
LBS9
SBS1
SBS9
1
0
9
0
1
0
9
0
9-1,
Figure
LBS0
LBS8
SBS0
SBS8
0
8
0
8
0
0
0
0
9-2, and