DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 117

IC CTRLR HDLC 256-CHANNEL 256BGA

DS31256

Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS31256

Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers
and their associated descriptors are ready for transmission. A set of internal addresses within the device
that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit
pending queue. On initialization, the host configures all of the registers shown in
initialization, the DMA only writes to (changes) the read pointers and the host only writes to the write
pointers.
Empty Case
The transmit pending queue is considered empty when the read and write pointers are identical.
Transmit Pending-Queue Empty State
Full Case
The transmit pending queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Transmit Pending-Queue Full State
Table 9-J. Transmit Pending-Queue Internal Address Storage
Note: Transmit free-queue end address is not an absolute address. The absolute end address is “Base + TPQEA.”
read pointer >
read pointer >
Transmit Pending-Queue Base Address 0 (lower word)
Transmit Pending-Queue Base Address 1 (upper word)
Transmit Pending-Queue Host Write Pointer
Transmit Pending-Queue DMA Read Pointer
Transmit Pending-Queue End Address
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
REGISTER
valid descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
< write pointer
< write pointer
117 of 183
TPQBA0
TPQBA1
TPQWP
TPQEA
TPQRP
NAME
ADDRESS
080Ch
0800h
0804h
0810h
0808h
Table
9-J. After

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