DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 63

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Repetitive Pattern Length Map
Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either
the bit counter or the error counter overflows.
Bit 14/Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an interrupt if a bit
error is detected.
Bit 15/Interrupt Enable for Change-of-Synchronization Status (IESYNC). Allows the receive BERT to cause
an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT either goes into or out
of synchronization).
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with repetitive or
pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever the host
wishes to load a new pattern. Must be cleared and set again for subsequent loads.
Bit 4/Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set
again for a subsequent bit error to be inserted.
Bit 5/Error Insert Bit 0 (EIB0); Bit 6/Error Insert Bit 1 (EIB1); Bit 7/Error Insert Bit 2 (EIB2).
Automatically inserts bit errors at the prescribed rate into the generated data pattern. Useful for verifying error
detection operation.
Length
17 Bits
21 Bits
25 Bits
29 Bits
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
Code
0000
0100
1000
1100
EIB2
15
7
0
0
BERTC1
BERT Control Register 1
0504h
EIB1
Length
18 Bits
22 Bits
26 Bits
30 Bits
14
6
0
0
EIB0
Code
0001
0101
1001
1101
13
5
0
0
Alternating Word Count
SBE
12
4
0
0
63 of 183
Length
19 Bits
23 Bits
27 Bits
31 Bits
n/a
11
3
0
0
Code
0010
0110
1010
1101
n/a
10
2
0
0
Length
20 Bits
24 Bits
28 Bits
32 Bits
n/a
1
9
0
0
Code
0011
0111
1011
1111
TC
0
0
8
0