DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 49

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port 0 (1 or 2) Layer 1 state machine logic is
defeated, and RC0 (1, 2) and RD0 (1, 2) are routed to some dedicated high-speed HDLC processing logic. Only
present in RP0CR, RP1CR, and RP2CR. Bit 8 is not assigned in ports 3 through 15.
Bit 9/Unchannelized Enable (RUEN). When enabled, this bit forces the port to operate in an unchannelized
fashion. When disabled, the port operates in a channelized mode.
Bit 10/Local Loopback Enable (LLB). This loopback routes transmit data back to the receive port. It can be used
in both channelized and unchannelized port operating modes, even on ports 0, 1, and 2 operating at speeds up to
52MHz
local loopback (CLLB) function. See Section
Bit 12/V.54 Time Out (VTO). This read-only bit reports the real-time status of the V.54 detector. It is set to 1
when the V.54 detector has finished searching for the V.54 loop-up pattern and has not detected it. This indicates
to the host that the V.54 detector can now be used to search for the V.54 loop-up pattern on other HDLC channels,
and the host can initiate this by configuring the RV54 bits in the RP[n]CR register and then toggling the VRST
control bit. See Section
Bit 13/V.54 Loopback (VLB). This read-only bit reports the real-time status of the V.54 detector. It is set to 1
when the V.54 detector has verified that a V.54 loop-up pattern has been seen. When set, it remains set until either
the V.54 loop-down pattern is seen or the V.54 detector is reset by the host (i.e., by toggling VRST). See
Section
Bit 14/Interrupt Enable for RCOFA (IERC)
Bit 15/COFA Status Bit (RCOFA). This latched read-only status bit sets if a COFA is detected. The COFA is
detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the
193/256/512/1024-bit frame. This bit resets when read and does not set again until another COFA has occurred.
Transmit-Side Control Bits (one each for all 16 ports)
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
0 = disabled
1 = enabled
0 = channelized mode
1 = unchannelized mode
0 = loopback disabled
1 = loopback enabled
6.4
0 = interrupt masked
1 = interrupt enabled
(Figure
for more details on how the V.54 detector operates.
TCOFA
TSS1
15
6-1). In channelized applications, a per-channel loopback can be realized by using the channelized
7
0
0
6.4
TP[n]CR, where n = 0 to 15 for each port
Transmit Port [n] Control Register
See the Register Map in Section 4.
TSS0
IETC
for more details about how the V.54 detector operates.
14
6
0
0
TSD1
n/a
13
5
0
0
6.3
for details on CLLB.
TSD0
n/a
12
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4
0
0
TFDA1
TUBS
11
3
0
0
UNLB
TISE
10
2
0
0
TUEN
TIDE
1
0
9
0
TP[i]HS
TICE
0
8
0
0