DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 80

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to the internal transmit starting
block pointer RAM, this bit should be written to 1 by the host. This causes the device to take the data that is in the
TFSBP register and write it to the channel location indicated by the HCID bits. When the device has completed the
write, the IAB is set to 0.
Note: The TFSBP register is write-only memory. Once this register has been written to and the operation has
started, the DS31256 internal state machine changes the value in this memory.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation has completed.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/Starting Block Pointer (TSBP0 to TSBP9). These bits determine which of the 1024 blocks within the
transmit FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of
the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these bits
are read, they report the current block pointer being used to read data from the transmit FIFO by the HDLC Layer
2 engines.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
0000000000 (000h) = use block 0 as the starting block
0111111111 (1FFh) = use block 511 as the starting block
1111111111 (3FFh) = use block 1023 as the starting block
BLKID7
TSBP7
IAB
n/a
15
15
7
7
0
0
TFSBP
Transmit FIFO Starting Block Pointer
0984h
TFBPIS
Transmit FIFO Block Pointer Indirect Select
0990h
BLKID6
TSBP6
IARW
n/a
14
14
6
6
0
0
BLKID5
TSBP5
n/a
n/a
13
13
5
5
0
0
BLKID4
TSBP4
n/a
n/a
12
12
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4
4
0
0
BLKID3
TSBP3
n/a
n/a
11
11
3
3
0
0
BLKID2
TSBP2
n/a
n/a
10
10
2
2
0
0
BLKID1
BLKID9
TSBP1
TSBP9
1
9
1
0
9
0
BLKID0
BLKID8
TSBP0
TSBP8
0
8
0
8
0
0