DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 76

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
8.1.1 Receive High Watermark
The high watermark tells the device how many blocks the HDLC engines should write into the receive
FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before it should
be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available
data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected. For
example, if four blocks were link-listed together and the host programmed the high watermark to three
blocks, then the DMA would read the data out of the FIFO and transfer it to the PCI bus after the HDLC
controller had written three complete blocks in succession into the FIFO and still had one block left to
fill. The DMA would not read the data out of the FIFO again until another three complete blocks had
been written into the FIFO in succession by the HDLC engine or until an EOF was detected. In this
example of four blocks being link-listed together, the high watermark could also be set to 1 or 2, but no
other values would be allowed. If an incoming packet does not fill the FIFO enough to reach the high
watermark before an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does
not wait for additional data to be written into the FIFO by the HDLC engines.
8.1.2 Transmit Low Watermark
The low watermark tells the device how many blocks should be left in the FIFO before the DMA should
begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be
filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available
data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For
example, if five blocks were link-listed together and the host programmed the low watermark to two
blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC
engine has read three complete blocks in succession from the FIFO and, therefore, still had two blocks
left before the FIFO was empty. The DMA would not read the data from the PCI bus again until another
three complete blocks had been read from the FIFO in succession by the HDLC engines. In this example
of five blocks being link-listed together, the low watermark could also be set to any value from 1 to 3
(inclusive) but no other values would be allowed. In other words, the tranmist low watermark can be set
to a value of 1 to N - 2, where N = number of blocks linked together. When a new packet is written into a
completely empty FIFO by the DMA, the HDLC engines wait until the FIFO fills beyond the low
watermark or until an EOF is seen before reading the data out of the FIFO.
8.2 FIFO Register Description
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
HCID7
IAB
15
7
0
0
HCID6
RFSBPIS
Receive FIFO Starting Block Pointer Indirect Select
0900h
IARW
14
6
0
0
HCID5
n/a
13
5
0
0
HCID4
n/a
12
76 of 183
4
0
0
HCID3
n/a
11
3
0
0
HCID2
n/a
10
2
0
0
HCID1
n/a
1
0
9
0
HCID0
n/a
0
8
0
0