DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 101

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only, all other bits are read-write.
Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system
reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be
activated (RDQFE = 1), then the host must first configure the timer to a proper state and then set the RDQFE bit to
one.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only, all other bits are read-write.
Bit 0/Receive Free-Queue FIFO Enable (RFQFE). See Section
Bit
Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). See Section
Bit 4/Receive Done-Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors to the done
queue, this bit must be set to 1. If this bit is set to 0, messages are written one at a time.
Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is
flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.
2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). See Section
0000h = illegal setting
0001h = timer count resets to 1
FFFFh = timer count resets to 65,536
0 = done-queue burst-write disabled
1 = done-queue burst-write enabled
0 = FIFO in normal operation
1 = FIFO is flushed
TC15
TC7
15
7
0
0
n/a
n/a
15
7
0
0
RDQFFT
Receive Done-Queue FIFO Flush Timer
0744h
RDMAQ
Receive DMA Queues Control
0780h
TC14
TC6
14
6
0
0
n/a
n/a
14
6
0
0
TC13
TC5
RDQF
13
5
0
0
n/a
13
5
0
0
RDQFE
TC12
TC4
101 of 183
12
4
0
0
n/a
12
4
0
0
TC11
RFQSF
TC3
11
3
0
0
n/a
9.2.3
11
3
0
0
for details.
RDQT2
RFQLF
TC10
TC2
10
2
0
0
9.2.3
10
2
0
0
9.2.3
for details.
for details.
RDQT1
TC1
TC9
1
0
9
0
n/a
1
0
9
0
RDQT0
RFQFE
TC0
TC8
0
8
0
0
0
0
8
0