DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 72

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0/Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine generates flags and
the FCS (if enabled through TCRC0/1) and performs zero stuffing. When this bit is set high, the HDLC engine
does not generate flags or the FCS and does not perform zero stuffing.
Bit 1/Transmit Interfill Select (TIFS)
Bits 2, 3/Transmit CRC Selection (TCRC0/TCRC1). These bits are ignored if the HDLC channel is set to
transparent mode (TTRANS = 1).
Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted
after being generated. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and
FCS) after the packet has been generated.
Bit 5/Transmit Bit Flip (TBF). When this bit is set low, the HDLC engine obtains the first HDLC bit to be
transmitted from the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When
this bit is set high, the HDLC engine obtains the first HDLC bit to be transmitted from the highest bit position of
the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]).
Bit 6/Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine allows the frame checksum
sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC engine inverts all the bits of
the FCS before transmission occurs. This is useful in debugging and testing HDLC channels at the system level.
Bit 7/Transmit Abort Enable (TABTE). When this bit is set low, the HDLC engine performs normally, only
sending an abort sequence (eight 1s in a row) when an error occurs in the PCI block or the FIFO underflows.
When this bit is set high, the HDLC engine continuously transmits an all-ones pattern (i.e., an abort sequence).
This bit is still active when the HDLC engine is configured in the transparent mode (TTRANS = 1).
TCRC1 TCRC0
0
0
1
1
0 = transparent mode disabled
1 = transparent mode enabled
0 = the interfill byte is 7Eh (01111110)
1 = the interfill byte is FFh (11111111)
0 = do not invert data
1 = invert all data (including flags and FCS)
0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the PCI bus
1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the PCI bus
0 = generate FCS normally
1 = invert all FCS bits
TABTE
n/a
15
0
1
0
1
7
No CRC is generated
16-bit CRC (CCITT/ITU Q.921)
32-bit CRC
Illegal state
THCD
Transmit HDLC Channel Definition
0484h
TCFCS
n/a
14
6
ACTION
TBF
n/a
13
5
TZSD
TID
12
72 of 183
4
TCRC1
TFG3
11
3
TCRC0
TFG2
10
2
TFG1
TIFS
1
9
TTRANS
TFG0
0
8