DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 147

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.
11.1 General Description
The local bus can operate in two modes, either as a PCI bridge (master mode) or as a configuration bus
(slave mode). This selection is made in hardware by connecting the LMS pin high or low.
shows an example of the local bus operating in the PCI bridge mode. In this example, the host can access
the control ports on the T1/E1 devices through the local bus.
PCI bridge mode, but the local bus arbitration is enabled, which allows a local CPU to control when the
host can have access to the local bus. To access the local bus, the host must first request the bus and then
wait until it is granted.
CPU on the local bus configures and monitors the DS31256. In this mode, the host on the PCI/custom
bus cannot access the DS31256 and the PCI/custom bus is only used to transfer HDLC packet data to
and from the host.
Table 11-A
operates only in a nonmultiplexed fashion; it is not capable of operating as a multiplexed bus. For both
operating modes, the local bus can be set up for either Intel or Motorola type buses. This selection is
made in hardware by connecting the LIM pin high or low.
Table 11-A. Local Bus Signals
Note: Signals shown in parentheses are active when Motorola mode (LIM = 1) is selected.
LHLDA (LBG)
LHOLD (LBR)
LWR (LR/W)
LRD (LDS)
LBGACK
SIGNAL
LD[0:15]
LA[0:19]
LRDY
LBHE
LCLK
LOCAL BUS
LINT
LMS
LIM
LCS
lists all the local bus pins and their applications in both operating modes. The local bus
Hold Acknowledge (Bus Grant)
Bus Write (Read/Write Select)
Hold Request (Bus Request)
Figure 11-3
Bus Read (Data Strobe)
Intel/Motorola Select
Bus Acknowledge
Byte High Enable
FUNCTION
Address Bus
Mode Select
Chip Select
Bus Ready
Bus Clock
Data Bus
Interrupt
features an example of the configuration mode. In this mode, the
147 of 183
Input on Read/Output on Write
MODE (LMS = 0)
PCI BRIDGE
Ignored
Output
Output
Output
Output
Output
Output
Output
Figure 11-2
Input
Input
Input
Input
Input
also shows an example of the
Input on Write/Output on Read
CONFIGURATION MODE
(LMS = 1)
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Ignored
Ignored
Output
Input
Input
Input
Input
Input
Input
Figure 11-1