DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 121

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The host reads from the transmit done queue to find which data buffers and their associated descriptors
have completed transmission. The transmit done queue is circular queue. A set of internal addresses
within the device that are accessed by both the host and the DMA keep track of the circular queue
addresses in the transmit done queue. On initialization, the host configures all of the registers, as shown
in
writes to the read pointer.
Empty Case
The transmit done queue is considered empty when the read and write pointers are identical.
Transmit Done-Queue Empty State
Full Case
The transmit done queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Transmit Done-Queue Full State
Table 9-K. Transmit Done-Queue Internal Address Storage
Transmit Done-Queue Base Address 0 (lower word)
Transmit Done-Queue Base Address 1 (upper word)
Transmit Done-Queue DMA Write Pointer
Transmit Done-Queue Host Read Pointer
Transmit Done-Queue End Address
Transmit Done-Queue FIFO Flush Timer
Note: Transmit done-queue end address is not an absolute address. The absolute end address is “Base + TDQEA x 4.”
read pointer >
read pointer >
Table
9-K. After initialization, the DMA only writes to (changes) the write pointer and the host only
REGISTER
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
< write pointer
< write pointer
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TDQBA0
TDQBA1
TDQFFT
TDQWP
TDQEA
TDQRP
NAME
ADDRESS
083Ch
0830h
0834h
0840h
0838h
0844h