DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 114

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.3.2 Packet Descriptors
A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in
main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed
anywhere in the 32-bit address space through the transmit descriptor base address
buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a
contiguous section of main memory. The host informs the DMA of data buffers’ actual sizes through the
byte count field that resides in the packet descriptor.
If an outgoing packet requires more space than the data buffer allows, then packet descriptors are link-
listed together by the host to provide a chain of data buffers.
descriptors were linked together for an incoming packet on HDLC channel 7. Channel 3 only required a
single data buffer and thus only one packet descriptor was used.
channels 5 and 1.
Packet descriptors can be either pending (i.e., queued up by the host and ready for transmission by the
DMA) or completed (i.e., have been transmitted by the DMA and are available for processing by the
host). Pending-packet descriptors are pointed to by the pending-queue descriptors and completed packet
descriptors are pointed to by the done-queue descriptors.
Table 9-I. Transmit Descriptor Address Storage
Figure 9-15. Transmit Descriptor Example
Transmit Descriptor Base Address 0 (lower word)
Transmit Descriptor Base Address 1 (upper word)
Done-Queue Descriptor Pointer
Pending-Queue Descriptor Address
Maximum of 65,536 Descriptors
REGISTER
Base + FFFD0h
Base + FFFF0h
114 of 183
Base + 00h
Base + 10h
Base + 20h
Base + 30h
Base + 40h
Base + 50h
Base + 60h
Base + 70h
Base + 80h
TDBA0
TDBA1
NAME
CH 7 Last Queued Buffer Descriptor
CH 7 1st Queued Buffer Descriptor
CH 5 Single Sent Buffer Descriptor
CH 7 2nd Queued Buffer Descriptor
CH 3 Single Queued Buffer Desc.
CH 7 Sent 1st Buffer Descriptor
CH 7 Last Sent Buffer Descriptor
Figure 9-15
Figure 9-10
Free Descriptor
Free Descriptor
Free Descriptor
Free Descriptor
ADDRESS
0850h
0854h
shows an example of how three
shows a similar example for
(Table
9-I). A data