DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 53

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/DS0 Channel Data (CHD0 to CHD15). This is the 16-bit data that is to either be written into or read
from the PORT RAM, specified by the CP[n]RDIS register.
Figure 6-4. Port RAM Indirect Access
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Note: In normal device operation, the host must never write to the C[n]DAT[j] registers.
Bits 0 to 7/Receive DS0 Data (RDATA). This register holds the most current DS0 byte received. It is used by the
transmit-side Layer 1 state machine when channelized network loopback (CNLB) is enabled.
CP[n]RDIS
CP[n]RD
CHD15
CHD7
15
15
7
0
0
7
CP[n]RD, where n = 0 to 15 for each port
Channelized Port [n] Register Data
See the Register Map in Section 4.
C[n]DAT[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0
Channelized Layer 1 DS0 Data Register
Indirect Access through CP[n]RD
CHD14
CHD6
14
14
6
0
0
6
Port RAM (one each for all 16 ports; n = 0 to 15)
C[n]DAT126
C[n]DAT127
C[n]DAT0
C[n]DAT1
C[n]DAT2
C[n]DAT3
C[n]DAT4
CHD13
CHD5
...
13
13
5
0
0
5
TDATA(8): Transmit DS0 Data
RDATA(8): Receive DS0 Data
CHD12
CHD4
R[n]CFG126
R[n]CFG127
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12
R[n]CFG0
R[n]CFG1
R[n]CFG2
R[n]CFG3
R[n]CFG4
12
4
0
0
4
...
CHD11
CHD3
11
11
3
0
0
3
T[n]CFG126
T[n]CFG127
T[n]CFG0
T[n]CFG1
T[n]CFG2
T[n]CFG3
T[n]CFG4
CHD10
CHD2
...
10
10
2
0
0
2
CHD1
CHD9
1
0
9
0
1
9
CHD0
CHD8
0
0
8
0
0
8