DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 84

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 9-A. DMA Registers to be Configured by the Host on Power-Up
ADDRESS
070C
071C
073C
080C
083C
0700
0704
0708
0710
0714
0718
0730
0734
0738
0740
0744
0750
0754
0770
0774
0780
0790
0794
0800
0804
0808
0810
0830
0834
0838
0840
0844
0850
0854
0870
0874
0880
RFQLBWP
RFQSBWP
RDMACIS
TDMACIS
RFQSBSA
RFQLBRP
RFQSBRP
RDQBA0
RDQBA1
TDQBA0
TDQBA1
RFQBA0
RFQBA1
RDQFFT
TPQBA0
TPQBA1
TDQFFT
RDMAC
RDMAQ
TDMAQ
RDQWP
TDQWP
TDMAC
RDQEA
TPQWP
TDQEA
RFQEA
RDQRP
RDBA0
RDBA1
TDQRP
TPQEA
TDBA0
TDBA1
NAME
TPQRP
RLBS
RSBS
Receive Free-Queue Base Address 0 (lower word)
Receive Free-Queue Base Address 1 (upper word)
Receive Free-Queue End Address
Receive Free-Queue Small Buffer Start Address
Receive Free-Queue Large Buffer Host Write Pointer
Receive Free-Queue Small Buffer Host Write Pointer
Receive Free-Queue Large Buffer DMA Read Pointer
Receive Free-Queue Small Buffer DMA Read Pointer
Receive Done-Queue Base Address 0 (lower word)
Receive Done-Queue Base Address 1 (upper word)
Receive Done-Queue End Address
Receive Done-Queue Host Read Pointer
Receive Done-Queue DMA Write Pointer
Receive Done-Queue FIFO Flush Timer
Receive Descriptor Base Address 0 (lower word)
Receive Descriptor Base Address 1 (upper word)
Receive DMA Configuration Indirect Select
Receive DMA Configuration (all 256 channels)
Receive DMA Queues Control
Receive Large Buffer Size
Receive Small Buffer Size
Transmit Pending-Queue Base Address 0 (lower word)
Transmit Pending-Queue Base Address 1 (upper word)
Transmit Pending-Queue End Address
Transmit Pending-Queue Host Write Pointer
Transmit Pending-Queue DMA Read Pointer
Transmit Done-Queue Base Address 0 (lower word)
Transmit Done-Queue Base Address 1 (upper word)
Transmit Done-Queue End Address
Transmit Done-Queue Host Read Pointer
Transmit Done-Queue DMA Write Pointer
Transmit Done-Queue FIFO Flush Timer
Transmit Descriptor Base Address 0 (lower word)
Transmit Descriptor Base Address 1 (upper word)
Transmit DMA Configuration Indirect Select
Transmit DMA Configuration (all 256 channels)
Transmit Queues FIFO Control
84 of 183
REGISTER
SECTION
9.2.3,
9.3.3,
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.4
9.2.4
9.2.4
9.2.4
9.2.4
9.2.4
9.2.2
9.2.2
9.2.5
9.2.5
9.2.1
9.2.1
9.3.3
9.3.3
9.3.3
9.3.3
9.3.3
9.3.4
9.3.4
9.3.4
9.3.4
9.3.4
9.3.4
9.3.2
9.3.2
9.3.5
9.3.5
9.2.4
9.3.4