DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 128

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the
transmit descriptor base address of the first transmit priority packet descriptor for the packet priority that is queued
up next for transmission.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
Bits 8 to 11/Transmit DMA Configuration RAM Word Select Bits 0 to 3 (TDCW0 to TDCW3)
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit DMA
configuration RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the
channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready
to be read from the TDMAC register, the IAB bit is set to 0. When the host wishes to write data to the internal
transmit DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to take the
data that is currently present in the TDMAC register and write it to the channel location indicated by the HCID
bits. When the device has completed the write, the IAB bit is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation has completed.
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
0000 = lower word of dword 0
0001 = upper word of dword 0
0010 = lower word of dword 1 (only word that the host can write to)
0011 = upper word of dword 1
0100 = lower word of dword 2
0101 = upper word of dword 2
0110 = lower word of dword 3
0111 = upper word of dword 3
1000 = lower word of dword 4
1001 = upper word of dword 4
1010 = lower word of dword 5
1011 = upper word of dword 5
HCID7
IAB
15
7
0
0
TDMACIS
Transmit DMA Configuration Indirect Select
0870h
HCID6
IARW
14
6
0
0
HCID5
n/a
13
5
0
0
HCID4
128 of 183
n/a
12
4
0
0
TDCW3
HCID3
11
3
0
0
TDCW2
HCID2
10
2
0
0
TDCW1
HCID1
1
0
9
0
TDCW0
HCID0
0
0
8
0