DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 12

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2-B. Initialization Steps
1)
2)
3)
4)
5)
6)
7)
8)
Table 2-C. Indirect Registers
Receive HDLC Channel Definition
Transmit HDLC Channel Definition
Receive DMA Configuration
Transmit DMA Configuration
Receive FIFO Staring Block Pointer
Receive FIFO Block Pointer
Receive FIFO High Watermark
Transmit FIFO Staring Block Pointer
Transmit FIFO Block Pointer
Transmit FIFO Low Watermark
Channelized Port
Initialize the PCI configuration registers
Initialize all indirect registers
Configure the device for operation
Enable the HDLC channels
Load the DMA descriptors
Enable the DMAs
Enable DMA for each HDLC channel
Enable data transmission
INITIALIZATION STEP
REGISTER
CP0RD to CP15RD
RFHWM
RDMAC
TDMAC
TFLWM
NAME
RFSBP
TFSBP
RHCD
THCD
RFBP
TFBP
12 of 183
Achieved by asserting the PIDSEL signal.
It is recommended that all of the indirect registers be set to
0000h
Program all necessary registers, which include the Layer 1,
HDLC, FIFO, and DMA registers.
Done through the RCHEN and TCHEN bits in the
R[n]CFG[j] and T[n]CFG[j] registers.
Indicate to the DMA where packet data can be written and
where pending data (if any) resides.
Done through the RDE and TDE control bits in the master
configuration (MC) register.
Done through the channel-enable bit in the receive and
transmit configuration RAM.
Set TFDA1 bit in TPnCR registers.
(Table
6144 (16 Ports x 128 DS0 Channels x 3
Registers for each DS0 Channel)
256 (one for each HDLC Channel)
256 (one for each HDLC Channel)
1536 (one for each HDLC Channel)
3072 (one for each HDLC Channel)
256 (one for each HDLC Channel)
1024 (one for each FIFO Block)
256 (one for each HDLC Channel)
256 (one for each HDLC Channel)
1024 (one for each FIFO Block)
256 (one for each HDLC Channel)
NUMBER OF INDIRECT REGISTERS
2-C).
COMMENTS