DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 19

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Signal Name:
Signal Description:
Signal Type:
This is a one-TC clock-wide synchronization pulse that can be applied to the DS31256 to force byte/frame
alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low (inverted
sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC
applied sync pulse can be during the first TC clock period of a 193/256/512/1024-bit frame or it can be applied
1/2, 1, or 2 TC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1
mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) TC clocks. It is acceptable to pulse
the TS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by
counting TC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should
be wired low.
Table 3-C. TS Sampled Edge
0 TC Clock Early Mode
1/2 TC Clock Early Mode
1 TC Clock Early Mode
2 TC Clock Early Mode
3.3 Local Bus Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal should be connected low when the device operates with no local bus access or if the local bus is used
as a bridge from the PCI bus. This signal should be connected high if the local bus is to be used by an external host
to configure the device.
Signal Name:
Signal Description:
Signal Type:
The signal determines whether the local bus operates in the Intel mode (LIM = 0) or the Motorola mode
(LIM = 1). The signal names in parentheses are operational when the device is in the Motorola mode.
Signal Name:
Signal Description:
Signal Type:
In PCI bridge mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When writing
data to the local bus, these signals are outputs and updated on the rising edge of LCLK. When reading data from
the local bus, these signals are inputs, which are sampled on the rising edge of LCLK. Depending on the assertion
of the PCI byte enables (PCBE0 to PCBE3) and the local bus-width (LBW) control bit in the local bus bridge
mode control register (LBBMC), this data bus uses all 16 bits (LD[15:0]) or just the lower 8 bits (LD[7:0]) or the
upper 8 bits (LD[15:8]). If the upper LD bits (LD[15:8]) are used, then the local bus high-enable signal (LBHE) is
asserted during the bus transaction. If the local bus is not currently involved in a bus transaction, all 16 signals are
tri-stated. When reading data from the local bus, these signals are outputs that are updated on the rising edge of
LCLK. When writing data to the local bus, these signals become inputs, which are sampled on the rising edge of
LCLK. In configuration mode (LMS = 1), the external host configures the device and obtains real-time status
0 = local bus is in the PCI bridge mode (master)
1 = local bus is in the configuration mode (slave)
0 = local bus is in the Intel mode
1 = local bus is in the Motorola mode
SIGNAL
TS0 to TS15
Transmit Serial Data Synchronization Pulse
Input
LMS
Local Bus Mode Select
Input
LIM
Local Bus Intel/Motorola Bus Select
Input
LD0 to LD15
Local Bus Nonmultiplexed Data Bus
Input/Output (tri-state capable)
NORMAL TC CLOCK MODE
Falling Edge
Falling Edge
Falling Edge
Rising Edge
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INVERTED TC CLOCK MODE
Falling Edge
Rising Edge
Rising Edge
Rising Edge
(Table
3-C). The