DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 40

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE). This status bit is set to 1 if any of the receive HDLC
channels experiences a CRC checksum error. The RCRCE bit is cleared when read and is not set again until
another CRC checksum error has occurred. If enabled through the RCRCE bit in the interrupt mask for SDMA
(ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also
at the LINT if the local bus is in configuration mode.
Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT). This status bit is set to 1 if any of the receive
HDLC channels detects an abort. The RABRT bit is cleared when read and is not set again until another abort has
been detected. If enabled through the RABRT bit in the interrupt mask for SDMA (ISDMA), the setting of this bit
causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in
configuration mode.
Bit 4/Status Bit for Receive HDLC Length Check (RLENC). This status bit is set to 1 if any of the HDLC
channels:
The RLENC bit is cleared when read and is not set again until another length violation has occurred. If enabled
through the RLENC bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware
interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration
mode.
Bit 5/Status Bit for Receive FIFO Overflow (ROVFL). This status bit is set to 1 if any of the HDLC channels
experiences an overflow in the receive FIFO. The ROVFL bit is cleared when read and is not set again until
another overflow has occurred. If enabled through the ROVFL bit in the interrupt mask for SDMA (ISDMA), the
setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if
the local bus is in configuration mode.
Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit is set to 1 each time the receive
DMA completes a single read or a burst read of the large buffer free queue. The RLBR bit is cleared when read
and is not be set again until another read of the large buffer free queue has occurred. If enabled through the RLBR
bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus
through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit is set to 1 each time the
receive DMA tries to read the large buffer free queue and it is empty. The RLBRE bit is cleared when read and is
not set again until another read of the large buffer free queue detects that it is empty. If enabled through the
RLBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI
bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode.
•
•
•
exceeds the octet length count (if so enabled to check for octet length)
receives an HDLC packet that does not meet the minimum length criteria of either 4 or 6 bytes
experiences a nonintegral number of octets between opening and closing flags
TDQWE
RLBRE
15
7
0
0
SDMA
Status Register for DMA
0028h
TDQW
RLBR
14
6
0
0
ROVFL
TPQR
13
5
0
0
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RLENC
TUDFL
12
4
0
0
RDQWE
RABRT
11
3
0
0
RCRCE
RDQW
10
2
0
0
RSBRE
n/a
1
0
9
0
RSBR
n/a
0
0
8
0