DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 20

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is
not available).
Signal Name:
Signal Description:
Signal Type:
In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to
indicate which address to be written to or read from. These signals are tri-stated when the local bus is not currently
involved in a bus transaction and driven when a bus transaction is active. In configuration mode
(LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active. The upper four (LA[19:16]) are
ignored and should be connected low.
Signal Name:
Signal Description:
Signal Type:
In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode
(LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal
determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel
mode (LIM = 0), it determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal
determines whether a read or write is to occur.
Signal Name:
Signal Description:
Signal Type:
In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel
mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising
edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel
mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the rising
edge writes data into the device.
Signal Name:
Signal Description:
Signal Type:
In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK.
If asserted and unmasked, this signal causes an interrupt at the PCI bus through the PINTA signal. If not used in
PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an open-
drain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal
remains low until either the interrupt is serviced or masked.
Signal Name:
Signal Description:
Signal Type:
This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete.
This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in
configuration mode (LMS = 1) and should be connected high.
LA0 to LA19
Local Bus Nonmultiplexed Address Bus
Input/Output (tri-state capable)
LWR (LR/W)
Local Bus Write Enable (Local Bus Read/Write Select)
Input/Output (tri-state capable)
LRD (LDS)
Local Bus Read Enable (Local Bus Data Strobe)
Input/Output (tri-state capable)
LINT
Local Bus Interrupt
Input/Output (open drain)
LRDY
Local Bus PCI Bridge Ready (PCI Bridge Mode Only)
Input
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