DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 29

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.6 HDLC Registers (4xx)
4.7 BERT Registers (5xx)
4.8 Receive DMA Registers (7xx)
ADDRESS
OFFSET/
ADDRESS
ADDRESS
OFFSET/
OFFSET/
0400
0404
0410
0480
0484
050C
051C
0500
0504
0508
0510
0514
0518
070C
071C
073C
0700
0704
0708
0710
0714
0718
0730
0734
0738
0740
0744
0750
0754
0770
0774
0780
0790
0794
RFQLBWP
RFQSBWP
RDMACIS
RFQSBSA
RFQLBRP
RHCDIS
RFQSBRP
THCDIS
BERTBC0
BERTBC1
RDQBA0
RDQBA1
BERTRP0
BERTRP1
BERTEC0
BERTEC1
RFQBA1
RDQFFT
NAME
RFQBA0
RDMAC
RDMAQ
RDQWP
RHCD
RDQEA
THCD
BERTC0
BERTC1
RDQRP
RHPL
RFQEA
RDBA0
RDBA1
NAME
NAME
RLBS
RSBS
Receive HDLC Channel Definition Indirect Select
Receive HDLC Channel Definition
Receive HDLC maximum Packet Length. One per device.
Transmit HDLC Channel Definition Indirect Select
Transmit HDLC Channel Definition
Receive Free-Queue Base Address 0 (lower word)
Receive Free-Queue Base Address 1 (upper word)
Receive Free-Queue End Address
Receive Free-Queue Small Buffer Start Address
Receive Free-Queue Large Buffer Host Write Pointer
Receive Free-Queue Small Buffer Host Write Pointer
Receive Free-Queue Large Buffer DMA Read Pointer
Receive Free-Queue Small Buffer DMA Read Pointer
Receive Done-Queue Base Address 0 (lower word)
Receive Done-Queue Base Address 1 (upper word)
Receive Done-Queue End Address
Receive Done-Queue Host Read Pointer
Receive Done-Queue DMA Write Pointer
Receive Done-Queue FIFO Flush Timer
Receive Descriptor Base Address 0 (lower word)
Receive Descriptor Base Address 1 (upper word)
Receive DMA Configuration Indirect Select
Receive DMA Configuration
Receive DMA Queues Control
Receive Large Buffer Size
Receive Small Buffer Size
BERT Control 0
BERT Control 1
BERT Repetitive Pattern Set 0 (lower word)
BERT Repetitive Pattern Set 1 (upper word)
BERT Bit Counter 0 (lower word)
BERT Bit Counter 1 (upper word)
BERT Error Counter 0 (lower word)
BERT Error Counter 1 (upper word)
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REGISTER
REGISTER
REGISTER
SECTION
SECTION
9.2.3/9.2.4
SECTION
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.3
9.2.4
9.2.4
9.2.4
9.2.4
9.2.4
9.2.4
9.2.2
9.2.2
9.3.5
9.3.5
9.2.1
9.2.1
6.6
6.6
6.6
6.6
6.6
6.6
6.6
6.6
7.2
7.2
7.2
7.2
7.2