DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 111

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 9-13. Transmit DMA Priority Packet Handling
Note 1: The start descriptor pointer field in the transmit DMA configuration RAM is used by both the normal and
priority pending queues.
Next Pending Descriptor Pointer
Last Pending Descriptor Pointer
Normal
Path if No
Priority
Packets
Had
Occurred
Standard Queue Pointers
Start Descriptor Pointer
Next Descriptor Pointer
1st Descriptor
(EOF=0/CV=0)
2nd Descriptor
(EOF=0/CV=0)
Last Descriptor
(EOF=1/CV=1)
Last Descriptor
(EOF=1/CV=0)
Standard
Packet Chain
Column 1
Service
Priority
Packets
Buffer 1
Packet 1
Buffer 2
Packet 1
Buffer 3
Packet 1
Buffer 1
Packet 2
See
Note 1
All Priority Packets Have Been Serviced
Transmit DMA Configuration RAM
1st Descriptor
(EOF=0/CV=0)
Last Descriptor
(EOF=1/CV=1)
Last Descriptor
(EOF=1/CV=0)
Priority
Packet Chain
Column 2
Next Pending Descriptor Pointer
Last Pending Descriptor Pointer
Priority Queue Pointers
Next Descriptor Pointer
111 of 183
Buffer 1
Pri. Packet 1
Buffer 2
Pri. Packet 1
Buffer 1
Pri. Packet 2
Last Descriptor
(EOF=1/CV=0)
PV = 1
Priority
Packet Chain
Column 3
Buffer 1
Pri. Packet 3
Next Pending
Descriptor Pointer
stored within the
Packet Descriptor
1st Descriptor
(EOF=0/CV=0)
2nd Descriptor
(EOF=0/CV=0)
Last Descriptor
(EOF=1/CV=0)
Priority
Packet Chain
Column 4
Buffer 3
Pri. Packet 4
Buffer 1
Pri. Packet 4
Buffer 2
Pri. Packet 4