AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 106
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.5.10
32054F–AVR32–09/09
Reset Controller
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated.
Table 10-4
Figure 10-5. Reset Controller block diagram
Reset sources are divided into hard and soft resets. Hard resets imply that the system could
have become unstable, and virtually all logic will be reset. The clock generator, which also con-
trols the oscillators, will also be reset. If the device is reset due to a power-on reset, or reset
occurred when the device was in a sleep mode that disabled the oscillators, the normal oscillator
startup time will apply.
A soft reset will reset most digital logic in the device, such as CPU, HSB, and PB modules, but
not the OCD system, clock generator, Watchdog Timer and RTC, allowing some functions,
including the oscillators, to remain active during the reset. The startup time from a soft reset is
thus negligible. Note that all PB registers are reset, except those in the RTC/WDT. The
MCCTRL and CKSEL registers are reset, and the device will restart using Oscillator 0 as clock
source for all synchronous clocks.
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
RESET_N
Power-On
Detector
lists these and other reset sources supported by the Reset Controller.
Watchdog Reset
NTAE
DBR
Controller
RC_RCAUSE
Reset
Hard Reset
Soft Reset
AT32AP7002
OCD, RTC/WDT
Clock Generato
CPU, HSB,
PBA, PBB
106
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