AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 750

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 34-5. STN Panel Timing, CLKMOD 0
32054F–AVR32–09/09
LCD_VSYNC
LCD_HSYNC
LCD_VSYNC
LCD_HSYNC
LCD_MODE
LCD_MODE
LCD_DVAL
LCD_PCLK
LCD_DVAL
LCD_PCLK
LCDD
LCDD
VHDLY+
There are two other parameters to configure in this module, the HOZVAL and the LINEVAL
fields of the LCDFRMCFG:
Figure
VSYNC signals:
•Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in
•Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP
•HOZVAL configures the number of active PCLK cycles in each line. The number of active
•LINEVAL configures the number of active lines per frame. This number is equal to
HPW+1
VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP. This field should
be programmed with 0 in STN Mode.
field of LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be
programmed with 0 in STN mode.
cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.
(LINEVAL+1) lines. The minimum value of this parameter is 1.
34-5,
HBP+1
Figure 34-6
1 PCLK
and
Line Period
Figure 34-7
Frame Period
1/2 PCLK 1/2 PCLK
show the timing of MODE, PCLK, DVAL, HSYNC and
HOZVAL+1
AT32AP7002
HFP+1
750