AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 67

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

PICOST.{D,W} – Store PICO Register(s)
Description
Stores the PICO register value(s) to the memory location specified by the addressing mode.
Operation:
I.
II.
III.
IV.
V.
VI.
Syntax:
I.
II.
III.
IV.
V.
VI.
Operands:
I-III.
IV-VI.
I-II, IV-V.p ∈ {0, 1, …, 15}
I, IV.
III, VI. {b, i} ∈ {0, 1, …, 15}
III, VI. sa ∈ {0, 1, 2, 3}
Opcode
I.
II.
32054F–AVR32–09/09
31
15
31
15
1
1
PICO CP#
PICO CP#
*(Rp + (ZE(disp8) << 2)) ← PrHi:PrLo;
*(Rp) ← PrHi:PrLo;
Rp ← Rp+8;
*(Rb + (Ri << sa2)) ← PrHi:PrLo;
*(Rp + (ZE(disp8) << 2)) ← Pr;
*(Rp) ← Pr;
Rp ← Rp-4;
*(Rb + (Ri << sa2)) ← Pr;
picost.d
picost.d
picost.d
picost.w
picost.w
picost.w
PrHi:PrLo ∈ {
Pr ∈ { INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A,
disp ∈ {0, 4, …, 1020}
30
14
30
14
1
1
COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG}
29
13
29
13
1
1
Rp++, PrHi:PrLo
Rp[disp], Pr
INPIX1:INPIX2, OUTPIX2:INPIX0, OUTPIX0:OUTPIX1, COEFF0_B:COEFF0_A,
COEFF1_B:COEFF1_A, COEFF2_B:COEFF2_A, VMU1_OUT:VMU0_OUT,
CONFIG:VMU2_OUT }
Rp[disp], PrHi:PrLo
Rb[Ri<<sa], PrHi:PrLo
Rp++, Pr
Rb[Ri<<sa], Pr
28
12
28
12
0
1
0
0
27
11
27
11
1
1
PrLo[3:1]
PrLo[3:1]
26
10
26
10
0
1
25
25
1
9
1
9
24
24
1
8
0
1
8
0
23
23
1
7
1
7
0
1
22
22
0
6
0
6
1
21
21
1
5
1
5
1
20
20
0
4
0
4
disp8
19
19
3
3
0
AT32AP7002
0
18
18
2
2
Rp
Rp
0
17
17
1
1
0
16
16
0
0
67