AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 332

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

22. PS/2 Module (PSIF)
22.1
22.2
22.3
22.3.1
22.3.2
22.3.3
22.4
22.4.1
32054F–AVR32–09/09
Features
Description
Product Dependencies
The PS/2 Protocol
I/O Lines
Power Management
Interrupt
Device to host communication
Rev: 1.0.0.2
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The PS/2 module provides host functionality allowing the MCU to interface PS/2 devices such as
keyboard and mice. The module is capable of both host-to-device and device-to-host
communication.
The PS/2 may be multiplexed with PIO lines. The programmer must first program the PIO con-
troller to give control of the pins to the PS/2 module.
The clock for the PS/2 module is generated by the power manager. The programmer must
ensure that the PS/2 clock is enabled in the power manager before using the PS/2 module.
The PS/2 module has an interrupt line connected to the interrupt controller. Handling the PS/2
interrupt requires programming the interrupt controller before configuring the PS/2 module.
The PS/2 protocol is a bidirectional synchronous serial communication protocol. It connects a
single master - referred to as the ‘host’ - to a single slave - referred to as the ‘device’. Communi-
cation is done through two lines called ‘data’ and ‘clock’. Both of these must be open-drain or
open-collector with a pullup resistor to perform a wired-AND function. When the bus is idle, both
lines are high.
The device always generates the clock signal, but the host may pull the clock low to inhibit trans-
fers. The clock frequency is in the range 10-16.7 kHz. Both the host and the slave may initiate a
transfer, but the host has ultimate control of the bus.
Data are transmitted one byte at a time in a frame consisting of 11-12 bits. The transfer format is
described in detail below.
The device can only initiate a transfer when the bus is idle. If the host at any time pulls the clock
low, the device must stop transferring data and prepare to receive data from the host.
The device transmits data using a 11-bit frame. The device writes a bit on the data line when the
clock is high, and the host reads the bit when the clock is low.
The format of the frame is:
PS/2 Host
Receive and transmit capability
Parity generation and error detection
Overrun error detection
AT32AP7002
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