AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 521

IC MCU 32BIT AVR32 196-CBGA

AT32AP7002-CTUT

Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Datasheets

Specifications of AT32AP7002-CTUT

Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32AP7002-CTUT
Manufacturer:
Atmel
Quantity:
10 000
27.7.2
Register Name:
Access Type:
Offset:
Reset Value:
• NCSRDPULSE: NCS Pulse Length in READ Access
• NRDPULSE: NRD Pulse Length
• NCSWRPULSE: NCS Pulse Length in WRITE Access
• NWEPULSE: NWE Pulse Length
32054F–AVR32–09/09
31
23
15
7
In standard read access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
In page mode read access, the NCSRDPULSE field defines the duration of the first access to one page.
In standard read access, the NRD signal pulse length is defined in clock cycles as:
The NRD pulse length must be at least one clock cycle.
In page mode read access, the NRDPULSE field defines the duration of the subsequent accesses in the page.
In write access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
The NWE signal pulse length is defined as:
The NWE pulse length must be at least one clock cycle.
Pulse Register
NCS Pulse Length in write access
NCS Pulse Length in read access
30
22
14
6
PULSE
Read/Write
0x04 + CS_number*0x10
0x01010101
NWE Pulse Length
NRD Pulse Length
29
21
13
5
=
=
(
(
256 NWEPULSE 6 [ ]
=
256 NRDPULSE 6 [ ]
=
(
(
256 NCSRDPULSE 6 [ ]
256 NCSWRPULSE 6 [ ]
×
×
28
20
12
4
×
×
NCSWRPULSE
NCSRDPULSE
NWEPULSE
NRDPULSE
+
27
19
11
+
3
NRDPULSE 5:0
NWEPULSE 5:0
+
+
NCSRDPULSE 5:0
NCSWRPULSE 5:0
[
[
26
18
10
2
]
]
) clock cycles
) clock cycles
[
[
]
]
) clock cycles
) clock cycles
25
17
9
1
AT32AP7002
24
16
8
0
521

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