AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 313

IC MCU 32BIT AVR32 196-CBGA

AT32AP7002-CTUT

Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Datasheets

Specifications of AT32AP7002-CTUT

Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32AP7002-CTUT
Manufacturer:
Atmel
Quantity:
10 000
Otherwise, the following equations determine the delay:
If FDIV is 0:
If FDIV is 1:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
If FDIV is 0:
If FDIV is 1:
32054F–AVR32–09/09
Delay Before SPCK
Delay Before SPCK
Delay Between Consecutive Transfers
Delay Between Consecutive Transfers
Note:
Note:
N = 32
N = 32
=
=
DLYBS
------------------ -
N
---------------------------- -
MCK
×
MCK
DLYBS
=
=
32
----------------------------------- -
32
---------------------------------------------- -
×
×
MCK
DLYBCT
N
MCK
×
DLYBCT
+
---------------- -
2MCK
SCBR
+
N
------------------------ -
2MCK
×
SCBR
AT32AP7002
313

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