AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 668

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

31.7.27
Name:
Access Type:
• CHANN_ENB (Channel Enable Command)
0 = DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the chan-
nel source bus is disabled at end of buffer.
If the DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the
corresponding CHANN_ENB bit to start the described transfer, if needed.
If the DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be
read and/or written reliably as soon as both DMASTATUS register CHANN_ENB and CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the
DMASTATUS register CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
1 = DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending
request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
0 = no channel register is loaded after the end of the channel transfer.
1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the DMASTA-
TUS/CHANN_ENB bit is reset.
If the DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary
• END_TR_EN: End of Transfer Enable (Control)
32054F–AVR32–09/09
BURST_LCK
LDNXT_DSC
31
23
15
–
7
0
0
1
1
USBA DMA Channelx Control Register
DESC_LD_IT
CHANN_ENB
30
22
14
–
6
0
1
0
1
END_BUFFIT
29
21
13
–
5
Description
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
Read/Write
END_TR_IT
28
20
12
–
4
BUFF_LENGTH
BUFF_LENGTH
DMACONTROLx
END_B_EN
27
19
11
–
3
END_TR_EN
26
18
10
–
2
LDNXT_DSC
AT32AP7002
25
17
9
–
1
CHANN_ENB
24
16
8
–
0
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