AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 606

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

31.6.5
Figure 31-5. Example of DMA Chained List:
31.6.6
31.6.6.1
32054F–AVR32–09/09
(Current Transfer Descriptor)
UDPHS Next Descriptor
DMA Channel Address
DMA Channel Control
UDPHS Registers
Memory Area
Data Buff 1
Data Buff 2
Data Buff 3
DMA
Handling Transactions with USB V2.0 Device Peripheral
Setup Transaction
USB packets of any length may be transferred when required by the USBA Device. These trans-
fers always feature sequential addressing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. These clock-cycle consuming memory row (or
bank) changes will then likely not occur, or occur only once instead of dozens times, during a
single big USB packet DMA transfer in case another HSB master addresses the memory. This
means up to 128-word single-cycle unbroken HSB bursts for Bulk endpoints and 256-word sin-
gle-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then
controlled by the lowest programmed USB endpoint size (EPT_SIZE bit in the EPTCFGx regis-
ter) and DMA Size (BUFF_LENGTH bit in the DMACONTROLx register).
The USBA device average throughput may be up to nearly 60 MBytes. Its internal slave average
access latency decreases as burst length increases due to the 0 wait-state side effect of
unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the exter-
nal DMA HSB bus slaves, each of both DMA HSB busses need less than 50% bandwidth
allocation for full USBA bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The USBA DMA Channel Transfer Descriptor is described in
Descriptor” on page 665
The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by
the application, the USBA accepts the next packets sent over the device endpoint.
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
”USBA DMA Channel Transfer
Transfer Descriptor
AT32AP7002
Null
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