AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 188
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
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Price
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32054F–AVR32–09/09
17. The DMACA fetches the next LLI from memory location pointed to by the current LLPx
Figure 17-13. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List
The DMA Transfer flow is shown in
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
register, and automatically reprograms the DARx, CTLx and LLPx channel registers.
Note that the SARx is not re-programmed as the reloaded value is used for the next DMA
block transfer. If the next block is the last block of the DMA transfer then the CTLx and
LLPx registers just fetched from the LLI should match Row 1 or Row 5 of
page
Address of
Source Layer
block complete interrupt is cleared by software. If the next block is to be the last block
in the DMA transfer, then the block complete ISR (interrupt service routine) should
clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into Row1 as
shown in
transfer, then the source reload bit should remain enabled to keep the DMACA in
Row 7 as shown in
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but starts
the next block transfer immediately. In this case, software must clear the source
reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of
176
176. The DMA transfer might look like that shown in
before the last block of the DMA transfer has completed.
Destination Address
SAR
Table 17-1 on page
Source Blocks
Table 17-1 on page
Figure 17-14 on page
176. If the next block is not the last block in the DMA
176.
DAR(N)
DAR(1)
DAR(2)
DAR(0)
Destination Blocks
BlockN
Block0
Block1
Block2
189.
Figure 17-13 on page
Destination Layer
Table 17-1 on page
AT32AP7002
Address of
Table 17-1 on
188.
188
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