AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 200

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

17.12.2
Name:
Access Type:
Offset:
Reset Value:
• DADD: Destination Address of DMA transfer
The starting System Bus destination address is programmed by software before the DMA channel is enabled or by a LLI
update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the desti-
nation address of the current System Bus transfer.
Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address
increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer.
32054F–AVR32–09/09
31
23
15
7
Channel x Destination Address Register
30
22
14
6
DARx
Read/Write
0x008 + [x * 0x58]
0x00000000
29
21
13
5
28
20
12
4
DADD[31:24]
DADD[23:16]
DADD[15:8]
DADD[7:0]
27
19
11
3
26
18
10
2
25
17
9
1
AT32AP7002
24
16
8
0
200