AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 507

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 27-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif-
Figure 27-25. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access
32054F–AVR32–09/09
Read2 controlling
Write2 controlling
Read1 controlling
Read1 controlling
NBS0, NBS1,
signal(NWE)
signal(NRD)
signal(NRD)
signal(NRD)
A0, A1
NBS0, NBS1,
CLK_SMC
A[25:2]
D[15:0]
A[25:2]
A0, A1
CLK_SMC
D[15:0]
ferent Chip Selects.
on Different Chip Selects.
TDFCYCLES = 6
• read access followed by a write access on another chip select.
• read access followed by a write access on the same chip select.
with no TDF optimization.
Read1 cycle
TDFCYCLES = 4
Read1 cycle
Read1 hold = 1
Read1 hold = 1
Chip Select Wait State
TDFCYCLES = 4
Read to Write
Wait State
TDFCYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
Write2 setup = 1
(optimization disabled)
TDFMODE=0
Write 2 cycle
AT32AP7002
(optimization disabled)
Read2 setup = 1
TDFMODE=0
Read 2 cycle
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