AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 185

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054F–AVR32–09/09
Figure 17-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers.
This put the DMACA into Row 1 as shown in
block is not the last block in the DMA transfer, then the reload bits should remain
enabled to keep the DMACA in Row 4.
masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware does
not stall until it detects a write to the block complete interrupt clear register but starts
the next block transfer immediately. In this case software must clear the reload bits in
the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the DMACA into
ROW 1 of
pleted. The transfer is similar to that shown in
transfer flow is shown in
Source Layer
Address of
Table 17-1 on page 176
SAR
Source Blocks
Figure 17-12 on page
before the last block of the DMA transfer has com-
Block2
Block0
Block1
BlockN
Destination Blocks
Table 17-1 on page
Figure 17-11 on page
186.
Destination Layer
DAR
Address of
AT32AP7002
176. If the next
185. The DMA
185