AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 28

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

7.4
7.5
7.5.1
7.5.2
32054F–AVR32–09/09
Vector Multiplication Unit (VMU)
Input Pixel Selector
Transformation Mode
Horizontal Filter Mode
Each VMU consists of three multipliers used for multiplying unsigned 8-bit pixel components with
signed 12-bit coefficients.The result from each multiplication is a 20-bit signed number that is
input to a 22-bit vector adder along with an offset as shown in
ation is equal to the offsetted vector multiplication given in the following equation:
Figure 7-2.
The Input Pixel Selector uses the ISM (Input Selection Mode) field in the CONFIG register and
the three input pixel source addresses given in the PICO operation instructions to decide which
pixels to select for inputs to the VMUs.
When the Input Selection Mode is set to Transformation Mode the input pixel source addresses
INx, INy and INz directly maps to three pixels in the INPIXn registers. These three pixels are
then input to each of the VMUs. The following expression then represents what is computed by
the VMUs in Transformation Mode:
In Horizontal Filter Mode the input pixel source addresses INx, INy and INz represents the base
pixel address of a pixel triplet. The pixel triplet {IN(x), IN(x+1), IN(x+2)} is input to VMU0, the
pixel triplet {IN(y), IN(y+1), IN(y+2)} is input to VMU1 and the pixel triplet {IN(z), IN(z+1), IN(z+2)}
offsetn
VMU0_OUT
VMU1_OUT
VMU2_OUT
Inside VMUn (n ∈ {0,1,2})
=
coeffn_0
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
vmu_out
Multiply
vmun_in0
=
coeff0 coeff1 coeff2
coeffn_1
Vector Adder
vmun_out
Multiply
vmun_in1
vmu_in0
vmu_in1
vmu_in2
INx
INy
INz
+
Figure 7-2 on page
OFFSET0 or VMU0_OUT
OFFSET1 or VMU1_OUT
OFFSET2 or VMU2_OUT
+
offset
coeffn_2
AT32AP7002
Multiply
vmun_in2
VMUn
28. The oper-
28