AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 251

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

19.5.8
19.5.9
Figure 19-5. Input Glitch Filter Timing
19.5.10
32054F–AVR32–09/09
if IFSR = 0
if IFSR = 1
CLK_PIO
Pin Level
PDSR
PDSR
Inputs
Input Glitch Filtering
Input Change Interrupt
1 cycle
The level on each I/O line can be read through PDSR (Pin Data Status Register). This register
indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input
or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch filters are independently programmable on each I/O line. When the glitch fil-
ter is enabled, a glitch with a duration of less than 1/2 CLK_PIO cycle is automatically rejected,
while a pulse with a duration of 1 CLK_PIO cycle or more is accepted. For pulse durations
between 1/2 CLK_PIO cycle and 1 CLK_PIO cycle the pulse may or may not be taken into
account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must
exceed 1 CLK_PIO cycle, whereas for a glitch to be reliably filtered out, its duration must not
exceed 1/2 CLK_PIO cycle. The filter introduces one CLK_PIO cycle latency if the pin level
change occurs before a rising edge. However, this latency does not appear if the pin level
change occurs before a falling edge. This is illustrated in
The glitch filters are controlled by the register set; IFER (Input Filter Enable Register), IFDR
(Input Filter Disable Register) and IFSR (Input Filter Status Register). Writing IFER and IFDR
respectively sets and clears bits in IFSR. This last register enables the glitch filter on the I/O
lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.
It acts only on the value read in PDSR and on the input change interrupt detection. The glitch fil-
ters require that the PIO Controller clock is enabled.
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing IER (Interrupt Enable Register)
and IDR (Interrupt Disable Register), which respectively enable and disable the input change
interrupt by setting and clearing the corresponding bit in IMR (Interrupt Mask Register). As Input
change detection is possible only by comparing two successive samplings of the input of the I/O
line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regard-
less of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO
Controller or assigned to a peripheral function.
1 cycle
up to 1.5 cycles
1 cycle
up to 2.5 cycles
2 cycles
Figure
19-5.
AT32AP7002
up to 2 cycles
1 cycle
1 cycle
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