AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 808

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

35.5.2
Table 35-3.
32054F–AVR32–09/09
Mode
Data Ordering
RGB Format in Default Mode, RGB_CFG = 00, No Swap
Byte
face, thereby reducing the pin count. In order to retrieve both frame and line synchronization
properly, at least one line of vertical blanking is mandatory.
Figure 35-3. HSYNC and VSYNC Synchronization
Figure 35-4. SAV and EAV Sequence Synchronization
The RGB color space format is required for viewing images on a display screen preview, and the
YCbCr color space format is required for encoding.
All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows
the user to program the same component order as the sensor, reducing software treatments to
restore the right format.
Table 35-2.
Mode
Default
Mode1
Mode2
Mode3
DATA[7..0]
ISII_PCK
D7
ISI_HSYNC
ISI_VSYNC
DATA[7..0]
ISI_PCK
Data Ordering in YCbCr Mode
D6
FF
00
SAV
00
80
D5
Byte 0
Cb(i)
Cr(i)
Y(i)
Y(i)
1 line
Y
Y
Cb
Cb
Y
Y
D4
Cr
Cr
Y
Y
Byte 1
Y(i)
Y(i)
Cb(i)
Cr(i)
Active Video
Cb
Frame
Cb
Y
D3
Cr
Y
Y
Cr
Y
D2
Byte 2
Cr(i)
Cb(i)
Y(i+1)
Y(i+1)
Cb
Y
Cr
Y
Y
Cr
AT32AP7002
Cb FF
D1
Byte 3
Y(i+1)
Y(i+1)
Cr(i)
Cb(i)
00
EAV
00
D0
9D
808