AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 128
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
Quantity
Price
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13. Interrupt Controller (INTC)
13.1
13.2
13.3
32054F–AVR32–09/09
Features
Overview
Block Diagram
Rev: 1.0.0.4
•
•
The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an inter-
rupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for
regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).
The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request
lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register
(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and
an autovector to each group, and the IRRs are used to identify the active interrupt request within
each group. If a group has only one interrupt request line, an active interrupt group uniquely
identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC
also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the
group that has a pending interrupt of the corresponding priority level. If several groups have a
pending interrupt of the same level, the group with the lowest number takes priority.
Figure 13-1
accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the
NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of
the figure.
Autovectored low latency interrupt service with programmable priority
Up to 64 groups of interrupts with up to 32 interrupt requests in each group
– 4 priority levels for regular, maskable interrupts
– One Non-Maskable Interrupt
gives an overview of the INTC. The grey boxes represent registers that can be
AT32AP7002
128
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