AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 752

IC MCU 32BIT AVR32 196-CBGA

AT32AP7002-CTUT

Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Datasheets

Specifications of AT32AP7002-CTUT

Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32AP7002-CTUT
Manufacturer:
Atmel
Quantity:
10 000
34.6.2.10
34.6.2.11
32054F–AVR32–09/09
Display
PWM
HFP
In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The
number_data_lines is equal to the number of bits of the interface in single scan mode;
number_data_lines is equal to half the bits of the interface in dual scan mode.
In color mode, Horizontal_display_size equals three times the number of horizontal pixels.
In TFT Mode:
The frame rate equation is used first without considering the clock periods added at the end
beginning or at the end of each line to determine, approximately, the PCLK rate:
With this value, the CLKVAL is fixed, as well as the corresponding PCLK rate.
Then select VHDLY, HPW and HBP according to the type of LCD used and
page
Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value:
The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINE-
CNT field decreases by one unit at each falling edge of hsync.
This block is used to configure the polarity of the data and control signals. The polarity of all
clock signals can be configured by LCDCON2[12:8] register setting.
The block also generates the LCD_PWR output that can be used to turn the LCD module on and
off by software. This signal is controlled by the PWRCON register and respects the number of
frames configured in the GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the
write access to LCD_PWR field (PWRCON[0]) and the activation/deactivation of LCD_PWR out-
put signal. The minimum value for the GUARD_TIME field is one frame. This gives the DMA
Controller enough time to fill the FIFOs before the start of data transfer to the LCD.
This block generates the LCD contrast control signal (CC) to make possible the control of the
display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be
converted to an analog voltage with a simple passive filter.
The PWM module has a free-running counter whose value is compared against a compare reg-
ister (CONTRAST_VAL register). If the value in the counter is less than that in the register, the
output brings the value of the polarity (POL) bit in the PWM control register: CONTRAST_CTR.
Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width propor-
tional to the value in the compare register is generated.
=
f
pclk
749.
×
-------------------------------------------------------------------------------------------------------- -
f
lcd_vsync
LINEVAL
HOZVAL
LINEVAL
f
lcd_pclk
×
(
=
LINEVAL
=
=
=
(
HOZVAL
Horizontal_display_size 1
Vertical_display_size 1
Vertical_display_size 1
1
+
VBP
+
5
)
+
×
(
VFP
f
lcd_vsync
+
1
)
×
(
(
LINEVAL
VHDLY
+
+
VPW
1
)
)
+
AT32AP7002
VBP
+
”Equation 1” on
HOZVAL
+
5
752
)

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