AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 777

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

34.13.9
Name: DMA2DCFG
Access: Read/Write
Reset value: 0x00000000
• ADDRINC: DMA 2D Addressing Increment
When 2-D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes
that the DMA controller must jump between screen lines. It must be programmed as: [({address of first 32-bit word in a
screen line} - {address of last 32-bit word in previous line})]. In other words, it is equal to 4*[number of 32-bit words occu-
pied by each line in the complete frame buffer minus the number of 32-bit words occupied by each displayed line]. Bit
DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA control-
ler use this new value.
• PIXELOFF: DAM2D Addressing Pixel offset
When 2D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the offset of the first
pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31,
so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register
DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When
using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of
this field always selects the pixel in the same relative position within the word, independently of the memory ordering con-
figuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the
DMA controller use this new value.
32054F–AVR32–09/09
31
23
15
7
LCD DMA 2D Addressing Register
30
22
14
6
29
21
13
5
28
20
12
4
ADDRINC
ADDRINC
-
27
19
11
3
PIXELOFF
26
18
10
2
AT32AP7002
25
17
9
1
24
16
8
0
777