AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 640

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

31.7.11
Name:
Access Type:
• SPEED_CFG: Speed Configuration
Read/Write:
Speed Configuration:
• TST_J: Test J Mode
Read and write:
0 = no effect.
1 = set to send the J state on the USBA line. This enables the testing of the high output drive level on the D+ line.
• TST_K: Test K Mode
Read and write:
0 = no effect.
1 = set to send the K state on the USBA line. This enables the testing of the high output drive level on the D- line.
• TST_PKT: Test Packet Mode
Read and write:
0 = no effect.
1 = set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye pat-
terns, jitter, and any other dynamic waveform specifications.
32054F–AVR32–09/09
00
01
10
11
31
23
15
–
–
–
7
–
USBA Test Register
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then
to automatically switch to High Speed mode
Reserved
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will
not respond to a High Speed reset handshake
30
22
14
–
–
–
6
–
OPMODE2
29
21
13
–
–
–
5
TST
Read/Write
TST_PKT
28
20
12
–
–
–
4
TST_K
27
19
11
–
–
–
3
TST_J
26
18
10
–
–
–
2
AT32AP7002
25
17
–
–
9
–
1
SPEED_CFG
24
16
–
–
8
–
0
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