AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 766

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

AT32AP7002
LCDTIM1 contains four fields which determine the vertical front porch, back porch, and pulse
width, as well as the vertical to horizontal delay. Assuming desired values for these four param-
eters of 12, 31, 2, and 2, respectively, these fields should be determined as follows:
VFP = (12); VBP = (31); VPW = (2 - 1); VHDLY= (2 - 1);
LCDTIM1 can then be written as follows:
LCDTIM1 = (VHDLY<<24) | (VPW<<16) | (VBP<<8) | (VFP<<0);
LCDTIM2 contains three fields which determine the horizontal front porch, pulse width, and back
porch. Assuming desired values of 16, 96, and 48, respectively, these fields should be deter-
mined as follows:
HFP = (16 - 1); HPW= (96 - 1); HBP = (48 - 1);
However, there is a problem with the calculated value of HPW (95) because the width of the
HPW field in LCDTIM2 is only 6 bits, which implies that the largest allowed value of HPW is 63.
Fortunately, the horizontal pulse width value of 96 specified in the LCD module data sheet is just
a typical value. The minimum allowed horizontal pulse width is specified as 10 in the LCD mod-
ule data sheet, so HPW can be recomputed using a horizontal pulse width of 10:
HPW = (10 - 1);
LCDTIM2 can then be written:
LCDTIM2 = (HFP << 21) | (HPW<<8) | (HBP<<0);
The LCD Frame Configuration Register contains two fields, LINEVAL and HOZVAL. LINEVAL is
computed by subtracting 1 from the vertical display size (in pixels):
LINEVAL = 480 - 1;
For a TFT display, HOZVAL is determined by subtracting 1 from the horizontal display size:
HOZVAL = 640 - 1;
LCDFRMCFG is then written as:
LCDFRMCFG = (HOZVAL<<21) | (LINEVAL<<0);
LCDMVAL determines the MODE toggle rate. For this display, MODE should toggle every
frame, so all bits written to LCDMVAL should be zero:
LCDMVAL = 0; // MODE toggle each frame
Finally, the BRSTLEN (Burst Length) and FRMSIZE (Frame Size) fields of the DMA Frame Con-
figuration Register must be determined. A desired burst length of 8 will be assumed:
BRSTLEN = 8 - 1;
The Frame Size is in units of 32-bit words, so it is determined by multiplying the number of pixels
in the display by the number of bits used for representing a pixel in memory and then dividing by
32:
FRMSIZE = ((640*480)*16) / 32;
DMAFRMCFG can then be written as follows:
DMAFRMCFG = (BRSTLEN<<24) | (FRMSIZE<<0);
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