LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 258
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
9.7 Receive process
Since the Interrupt bit in the descriptor of the last fragment is set, after committing the
status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,
which triggers the device driver to inspect the status information.
In this example the device driver cannot add new descriptors as long as the Ethernet
block has not incremented the TxConsumeIndex because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the hardware commits the status
for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager
can the device driver program the next (the fourth) descriptor. The fourth descriptor can
already be programmed before completely transmitting the first frame.
In this example the hardware adds the CRC to the frame. If the device driver software
adds the CRC, the CRC trailer can be considered another frame fragment which can be
added by doing another gather DMA.
Each data byte is transmitted across the MII interface as two nibbles. On the MII interface
the Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if
hardware CRC is enabled. Once transmission on the MII interface commences the
transmission cannot be interrupted without generating an underrun error, which is why
descriptors and data read commands are issued as soon as possible and pipelined.
For an RMII PHY, the data communication between the Ethernet block and the PHY is
communicated at half the data-width (2 bits) and twice the clock frequency (50 MHz). In
10 Mbps mode data will only be transmitted once every 10 clock cycles.
This section outlines the receive process including the activities in the device driver
software.
Device driver sets up descriptors
After initializing the receive descriptor and status arrays to receive frames from the
Ethernet connection, the receive datapath should be enabled in the MAC1 register and
the Control register.
During initialization, each Packet pointer in the descriptors is set to point to a data
fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the
descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt
bit allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the initialization and enabling of the receive datapath, all descriptors are owned by
the receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of the
receive datapath.
Rx DMA manager reads Rx descriptor arrays
When the RxEnable bit in the Command register is set, the Rx DMA manager reads the
descriptors from memory at the address determined by RxDescriptor and
RxProduceIndex. The Ethernet block will start reading descriptors even before actual
receive data arrives on the (R)MII interface (descriptor prefetching). The block size of the
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
258 of 792
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